Dynamic reconfiguration of deep neural networks for resource-constrained FPGA Edge accelerators

Executing resource intensive Deep Neural Networks (DNN) on resource constrained devices at the edge provides many benefits. Executing DNN at the edge reduces latency by processing data locally without the overhead of Cloud communications. This is critical for real-time or near real-time applications such as autonomous vehicles or critical IoT systems. Execution of DNN at the edge also enhances privacy by processing private data at the edge, and reducing the need to send sensitive data over the network. It also reduces bandwidth usage by minimizing data transfer and preserves network resources. It also contributes to increased autonomy and resilience of edge devices that can continue to operate when disconnected from the network. And finally by optimizing DNN for the edge, it allows DNN to operate within power constraints of the edge while maintaining performance. Achieving these benefits requires solving a number of research challenges related to resource constraints at the edge, model compression and optimization for the edge, latency and real-time processing, hardware-software co-design, scalability and flexibility, and development and deployment complexity.

To be able to process complex DNN at the edge, hardware acceleration with FPGA is a very promising approach. FPGA can be easily customised for a given DNN architecture, they provide high performance, can be configured to be more power efficient than GPU, and can be reconfigured for different DNN providing much needed flexibility. To address the above challenges, this paper proposes combining Edge orchestration techniques with DNN design frameworks that are able to accelerate the network design phase, optimize the DNN for the underlying edge devices in terms of size and energy, and convert the DNN to FPGA implementations providing hardware acceleration benefits at the edge.